1. Field of the Invention
This invention relates to a voltage-to-digital converter for providing a digital representation of a voltage input signal. In particular, this invention relates to a vernier adjustment that changes the resolution of the voltage-to-digital converters.
2. Description of the Prior Art
Voltage-to-digital converters are commonly used to convert a sensed parameter to a digital representation of the sensed parameter for immediate analysis or for transmission to a remote location. In control systems, a sensed parameter is measured and evaluated to determine appropriate control loop adjustments.
Typically, speed and accuracy are critical to effective operation of the control loop. Whenever speed and accuracy can be improved, the benefits are significant. Frick et al U.S. Pat. No. 4,791,352 entitled "Transmitter with Vernier Measurement" and co-pending application Ser. No. 07/175,627, filed Mar. 30, 1988 entitled "Measurement Circuit" provide significant improvements to the speed and resolution of parameter-to-digital converters by performing conversions with a plurality of charge packets which are accumulated in an integrator. The amount of charge in each packet is representative of a sensed parameter. The accumulated charge is compared to a reference level and the resulting output is used as a feedback signal to control the accumulation of charge packets in the integrator. The number of charge packets generated during a measurement cycle is representative of the sensed parameter. A digital representation of the sensed parameter is determined from the counted numbers.
Improved accuracy is accomplished in the Frick et al patent by adding a vernier adjustment to each measurement cycle. A vernier adjustment is an adjustment that changes the resolution of the voltage-to-digital converter. During a first part of the measurement cycle, a plurality of first charge packets are generated by a first excitation potential and provide a "coarse" adjustment of charge accumulated in the integrator. During a second part of the measurement cycle, a plurality of second charge packets are generated by a second excitation potential, smaller than the first. The amount of charge in each charge packet is varied with the excitation potential and therefore the plurality of second charge packets provide a "fine" adjustment of charge on the integrator. The fine adjustment provides a significantly more accurate digital result than the "coarse" adjustment.
The vernier arrangement of the Frick et al. patent provides an improved combination of speed and resolution, however, generating coarse and fine excitation potentials (using either resistive or capacitive voltage dividers, programmable gain operational amplifiers, or other voltage dividers) add considerable complexity and need for adjustments to the circuit. In order to provide convenient counting of charge packets, resistive voltage divider ratios must be adjusted to an integer number N and further match one another with the same number N in both dividers. There is thus a need to provide a vernier arrangement which has desirable speed and resolution features but does not require complex circuitry generating coarse and fine excitation potentials.